When a semiconductor device such as a metal-oxide-semiconductor field-effect transistor (MOSFET) is scaled down through various technology nodes, device packing density and device performance are challenged by device layout and isolation. In order to avoid leakage between neighboring devices (cells), the standard cell layout adopts dummy polycrystalline silicon (poly) segments formed on edges of a silicon oxide definition (OD) region such as an active region of a standard cell, i.e., poly-on-OD-edge (PODE).
As the semiconductor IC industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design have resulted in the development of three-dimensional (3D) devices such fin-like field effect transistors (FinFETs). Advantages of FinFET devices include reducing the short channel effect and higher current flow. However, conventional FinFET devices and methods of fabricating FinFET devices have not been entirely satisfactory in adopting the PODE for isolating two neighboring devices (cells).